DIGITAL-JU-CHIPS-2025-SG-LFA – Lab to Fab Accelerators for Advanced Packaging and Heterogeneous Integration

Publication date: 03 December 2025
Call opening date: 03 December 2025
Closing date: 25 February 2026 – 17:00 (GMT +2) POSTPONED : April or early May 2026.

This call supports Lab to Fab Accelerators through Simple Grant (SG) actions under the Digital Europe Programme, with the objective of accelerating the industrial deployment of advanced packaging and heterogeneous integration technologies in Europe.

Funded projects are expected to strengthen the transition from research and pilot lines to manufacturing, by supporting mature, industry-driven initiatives addressing bottlenecks in areas such as advanced packaging, chiplets, and system integration. The call contributes directly to reinforcing the European semiconductor value chain, improving competitiveness, scalability, and resilience.

Actions should demonstrate a high level of maturity and readiness, with a strong focus on implementation, impact, and alignment with the Chips JU Work Programme 2023–2027, notably under the Chips for Europe Initiative.

Key objectives include:

• Contributing to Europe’s strategic autonomy in microelectronics
• Accelerating the transition from lab-scale innovation to industrial production
• Supporting advanced packaging and heterogeneous integration capabilities
• Strengthening European semiconductor manufacturing ecosystems
• Reducing technological and financial barriers to scale-up

DIGITAL-JU-CHIPS-2025-CSA-LFA – Lab to Fab Accelerator Ecosystem (CSA)

Closing date: 25 February 2026 – 17:00 (GMT +2)

This call supports Coordination and Support Actions (CSA) under the Digital Europe Programme, with the objective of strengthening the Lab to Fab Accelerator ecosystem in Europe. It focuses on boosting cooperation across the semiconductor value chain, particularly to accelerate the industrial implementation of advanced packaging, chiplets, and heterogeneous integration technologies.

Funded actions will contribute to structuring, coordinating, and aligning stakeholders at European and national levels, supporting knowledge transfer from research to industrial deployment. The call targets activities such as ecosystem coordination, strategic planning, networking, dissemination, standardisation support, and policy dialogue, in line with the Chips Joint Undertaking Work Programme 2023–2027.

Key objectives include:

• Strengthening cooperation between research, industry, and innovation actors
• Accelerating the transition from laboratory research to industrial manufacturing
• Supporting advanced packaging, chiplets, and heterogeneous integration ecosystems
• Enhancing European strategic autonomy in semiconductor technologies
• Improving visibility, coordination, and impact of EU-funded initiatives

HORIZON-JU-CHIPS-2026-FT4-IA – AI-assisted Methods and Tools for Software-Defined Vehicle Engineering Automation

Publication date: 03 February 2026
Call opening date: 03 February 2026
Closing date: 03 March 2026 – 17:00 (GMT +2)

The activities must have their centre of gravity at TRL 6-7 at the end of the project.

This focus topic (IA) aims to develop and validate advanced AI-assisted methods and tools (including generative AI) and an open, extensible AI-assisted engineering platform/toolchain to automate and accelerate software engineering tasks for software-defined vehicles, with demonstration and evaluation of efficiency gains across the lifecycle, plus transferable best practices to other sectors.

"The vision behind this topic is to massively accelerate ECS engineering efficiency through software engineering automation based on an expanded use of AI-assisted methods and tools, by building upon a cohesive collaboration between humans (with their ability to innovate and create intuitive solutions) and AI (with its ability to propose solutions exploring huge search spaces and recognizing statistical patterns from large data). This focus topic shall lead to a stronger competitive position of Europe in ECS engineering worldwide and stimulate the uptake of AI-powered methods and tools for improved engineering efficiency, by still helping with better understanding and broader acceptance of such technologies."

Key priorities include :

• Advanced AI-assisted methods and tools, including generative AI, for the automation of software engineering tasks, from enhancing human efficiency and optimizing resource utilization to enabling complex data/problems analysis/interpretation and supporting intelligent decision-making. Such engineering tasks often involve multiple domains (e.g., modelling, control, data management, communication, mechatronics, etc.) and stakeholders, with the burden of daunting legacy integration, refactoring (e.g., to re-design and replace obsolete technology), and the compliance with specific standards, regulations and certifications.
• Open and extensible AI-assisted integrated platform, based on methodologies including AI-support, AI-based tools and toolchains, following a well-defined engineering process, including the integration with legacy tools. The platform shall provide flexible usage in small and large multi-domain and multi-stakeholder engineering teams, impacting existing and upcoming ECS engineering automation tools and their usage.
• Showcasing and evaluation for software-defined vehicles of efficiency enhancements in terms of cost and time for complex data/knowledge management, resource optimization, energy consumption, interoperability, product/process quality/trustworthiness, learning curve and usability, over the whole lifecycle, from design, through deployment, operations, and maintenance, to the product end-of-life and recycling, and its evolution.
• Best practices and small proof-of-concept studies for other sectors, e.g. medical/pharmaceutical and/or digital industry.

source : Chips JU Appendix 7 : activities launched in 2026 for the ECS Part

HORIZON-JU-CHIPS-2026-1-IA – IA Global call according to SRIA 2026

Publication date: 03 February 2026
Call opening date: 03 February 2026
Closing date, Stage 1: May 07, 2026 – 17:00 (GMT +2)

The activities have their centre of gravity at the TRL 5-8.

A Chips JU Innovation Action (IA) primarily consists of activities aiming at technology or method introduction, pilot lines, test beds, demonstrators, innovation pilots and zones of full-scale testing. These activities produce plans and arrangements or designs for new, altered, or improved products, processes, methods and tools or services. For this purpose, they may include prototyping, testing, demonstrating, piloting, large-scale product validation and market replication.

To maximize effective implementation of the Chips JU top-level objectives, the list of IA proposals to be retained for public funding should constitute a balanced portfolio of projects developing innovative technologies (as defined in the SRIA in the functional technology layers and cross-sectional technologies sections) and applying them in different domains (as defined in the SRIA in ECS key application areas section). The domains represent the demand side of technologies, and the development of new technologies represents the supply side of technologies.

Topics in the scope (with linked major challenges) are :

• Process technology, equipment, materials and manufacturing
• Components, modules and systems integration
• Embedded software and beyond
• System of Systems
• Edge Computing and Embedded Artificial Intelligence
• Connectivity
• Architecture and design: methods and tools
• Quality, reliability, safety and cybersecurity
• Mobility
• Energy
• Digital Industry
• Health and wellbeing
• Agrifood and natural resources
• Digital Society

source : Chips JU Appendix 7 : activities launched in 2026 for the ECS Part

HORIZON-JU-CHIPS-2026-1-RIA – RIA Global call according to SRIA 2026

Publication date: 03 February 2026
Call opening date: 03 February 2026
Closing date: 07 May 2026 – 17:00 (GMT +2)

The activities have their centre of gravity at TRL 3-4.

Chips JU Research and Innovation Action (RIA) primarily consists of activities aiming to establish new knowledge and/or to explore the feasibility of a new or improved technology, product, process, service, method, tool or solution. For this purpose, they may include applied research, technology development and/or method/tool and integration, testing and validation on a small-scale prototype in a laboratory or simulated environment.

In order to maximize effective implementation of the Chips JU top-level objectives, the list of RIA proposals to be retained for public funding shall constitute a balanced portfolio of projects developing innovative technologies (as defined in the SRIA in the functional technology layers and cross-sectional technologies sections) and applying them in different domains (as defined in the SRIA in key application areas section). The domains represent the demand side of technologies, and the development of new technologies represents the supply side of technologies.

Topics in the scope (with linked major challenges) are :

• Process technology, equipment, materials and manufacturing
• Components, modules and systems integration
• Embedded software and beyond
• System of Systems
• Edge Computing and Embedded Artificial Intelligence
• Connectivity
• Architecture and design: methods and tools
• Quality, reliability, safety and cybersecurity
• Mobility
• Energy
• Digital Industry
• Health and wellbeing
• Agrifood and natural resources
• Digital Society

source : Chips JU Appendix 7 : activities launched in 2026 for the ECS Part

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